Vincent BEROULLE - Home page

Vincent BEROULLE (French Homepage)

Ph'D, Full Professor
Grenoble Institute of Engineering and Management

Grenoble INP - LCIS
50 rue B. de Laffemas CS10054
26902 VALENCE Cedex 9 FRANCE

email: vincent.beroulle(at)lcis.grenoble-inp.fr
Phone: +334 75 75 9457

Head of CTSYS team
Head of Mistre Valence Master
Grenoble INP LCIS

Research Interests: Security and Safety of Heterogenous Systems

Key words : Security, Safety, FPGA Prototyping, Verification, Test, Fault Injection
Applications : RFID, Critical Systems (Aeronautic, etc)

Safe-Air Project Coordinator: "Safety Evaluation of Aircraft Systems using Virtual Platforms"

Industrial Partners: Thales Valence, AEDvices consulting
Academic Partners: LCIS, TIMA, LHC (Saint Etienne)

Safe-RFID Project Coordinator: "Dependability and Security of RFID Systems"

Vulnerability analysis of RFID systems
SystemC RFID Systems Model for Faults Simulation
Dependability improvement of RFID systems
Ph'D thesis of Gilles FRITZ and Omar ABDELMALEK

ANR LIESSE project "Laser-Induced fault Effects in Security-dedicated circuitS"

Industrial Partner: ST Microelectronics
Academic Partners: LIRMM, LCIS, TIMA, ENSME, ONERA

Coordinateur du projet EMNESS "European Master Network On Embedded System Security and Safety"

Academic Partners: University of Stuttgart, University of Freiburg, University of Pireaus, University of Barcelona (UPC), Politechnico de Torino

Current PhD Students supervision:

Hiep Manh DO, "Design of Secure Tags using ECC", December 2019
Nikos Foivos POLYCHONOUS, "Supervisor Design for Critical Embedded Systems", December 2019
Amir ALIPOUR, "Machine Learning for Modeling of PUF", October 2019

Julie ROUX, "Robustness Evaluation of Critical System using Cross-Layer Analysis"', since January 2018
Baptiste PESTOURIE, "UWB based Secure Ranging and LOCalization", since October 2017
Johan LAURENT, "Security Evaluation with Virtual Prototyping and Statistic Analysis of HW/SW Systems against Laser Attacks", since October 2017

Graduated PhD Students:

Arash NEIJAT, "Hardware Trojan Detection with Logic Masking Approaches", (2014-2019)
Jérémy DUBEUF, "ECC Side Channel Analysis and Countermeasure Implementation" , CIFRE Maxim IC (2014-2018)
Athanasios PAPADIMITRIOU, "RTL Modeling of Laser attacks for Early Evaluation of Secure ICs and Countermeasure Design" (2012-2015), ANR LIESSE Project

Omar ABDELMALEK, "DESIGN AND EMULATION OF ROBUST ARCHITECTURES FOR UHF RFID TAGS" (2011-2015), ANR Safe-RFID Project

Noémie BOHER, "Evaluation and Security Enhancement of Analog Integrated Circuits ", (2012-2015), PhD at ST Microelectronics

Gilles FRITZ, "Fault Simulation for the Evaluation of On-Line Testing in RFID Systems", defended the 10th December 2012

M. Youssef SERRESTOU, "Optimization of functional qualification thanks to mutation analysis", Defended in December 2008

M. Tu TRAN XUAN, LCIS and CEA-LETI collaboration, "Test Method and Design-for-Test of Asynchronous Networks-on-Chip: Application to ANOC Network.", Defended in February 2008.

M. Rami Khouri,"VHDL-AMS Behavioral modeling of RF link for simulation and optimization of RFID UHF systems", Defended in May 2007

M. Yves JOANNON, CIFRE ST Microelectronics, « Qualification and automatic generation of stimuli for AMS&RF SoC testing », Defended on April 2008.

Teaching at Grenoble INP Esisar

Key words: Digital Design, VHDL, FPGA, VHDL-AMS, Functional Verification, Safety, Security

Advanced Digital Architectures
Verification and test of embedded secured systems
Design of Analog and Mixed Systems
Design of VLSI CMOS Integrated Circuits
Hardware/Software co-design

Head of the international master MISTRE Valence.

List of Publications

Full Publication List

mise à jour le 31 août 2020

50, rue Barthélémy de Laffemas
BP54 26902 VALENCE Cedex 09 France
Tél : +33 (0)4 75 75 94 49