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> Thèmes > Sécurité des systèmes embarqués et distribués critiques > Organisation et membres

Vincent BEROULLE - Home page

                 Vincent BEROULLE (French Homepage)
Ph'D, Full Professor
Grenoble Institute of Engineering and Management

Grenoble INP - LCIS
50 rue B. de Laffemas CS10054
26902 VALENCE Cedex 9 FRANCE
email: vincent.beroulle(at)
Phone: +334 75 75 9457

Head of CTSYS team
Head of Mistre Valence Master
Grenoble INP LCIS

Research Interests: Security and Safety of Heterogenous Systems

Key words : Security, Safety, FPGA Prototyping, Verification, Test, Fault Injection
Applications : RFID, Critical Systems (Aeronautic, etc)
  • Safe-Air Project Coordinator: "Safety Evaluation of Aircraft Systems using Virtual Platforms"
Industrial Partners: Thales Valence, AEDvices consulting
Academic Partners: LCIS, TIMA, LHC (Saint Etienne)  
Vulnerability analysis of RFID systems
SystemC RFID Systems Model for Faults Simulation
Dependability improvement of RFID systems
Ph'D thesis of Gilles FRITZ and Omar ABDELMALEK
  • ANR LIESSE project "Laser-Induced fault Effects in Security-dedicated circuitS"
Industrial Partner: ST Microelectronics
Academic Partners: LIRMM, LCIS, TIMA, ENSME, ONERA  
  • Coordinateur du projet EMNESS "European Master Network On Embedded System Security and Safety"
Academic Partners: University of Stuttgart, University of Freiburg, University of Pireaus, University of Barcelona (UPC), Politechnico de Torino 

Current PhD Students supervision:

  • Hiep Manh DO, "Design of Secure Tags using ECC", December 2019
  • Nikos Foivos POLYCHONOUS, "Supervisor Design for Critical Embedded Systems", December 2019
  • Amir ALIPOUR, "Machine Learning for Modeling of PUF", October 2019 
  • Julie ROUX, "Robustness Evaluation of Critical System using Cross-Layer Analysis"', since January 2018
  • Baptiste PESTOURIE, "UWB based Secure Ranging and LOCalization", since October 2017
  • Johan LAURENT, "Security Evaluation with Virtual Prototyping and Statistic Analysis of HW/SW Systems against Laser Attacks", since October 2017

Graduated PhD Students:

Teaching at Grenoble INP Esisar

Key words: Digital Design, VHDL, FPGA, VHDL-AMS, Functional Verification, Safety, Security

  • Advanced Digital Architectures
  • Verification and test of embedded secured systems
  • Design of Analog and Mixed Systems
  • Design of VLSI CMOS Integrated Circuits
  • Hardware/Software co-design
Head of the international master MISTRE Valence.

List of Publications

mise à jour le 31 août 2020

Université Grenoble Alpes