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Vincent BEROULLE - Home page

                 Vincent BEROULLE (French Homepage)
Ph'D, Full Professor
Head of LCIS Laboratory
Grenoble Institute of Engineering and Management

Grenoble INP - LCIS
50 rue B. de Laffemas CS10054
26902 VALENCE Cedex 9 FRANCE
email: vincent.beroulle(at)
Phone: +334 75 75 9457

Grenoble INP LCIS

Research Interests: Security and Safety of Integrated Systems

Key words : Security, Safety, Fault Modeling, Fault injection,
Applications : RFID, Critical Systems
  • Coordinator of EMNESS project "European Master Network On Embedded System Security and Safety"
Academic Partners: University of Stuttgart, University of Freiburg, University of Pireaus, University of Barcelona (UPC), Politechnico de Torino, Grenoble INP Phelma 
  • LCIS co-head of Anaconda project, "Automated Cybersecurity Analysis with non Intrusive tools", October 2020
Industrial Partners: Ponant technologies, Rtone
Co-head in partner labs: Paolo Maistri (TIMA), Marie-Laure Potet (Verimag)
  • Safe-Air Project Coordinator: "Safety Evaluation of Aircraft Systems using Virtual Platforms"
Industrial Partners: Thales Valence, AEDvices consulting
Academic Partners: LCIS, TIMA, LHC (Saint Etienne)  
Vulnerability analysis of RFID systems
SystemC RFID Systems Model for Faults Simulation
Dependability improvement of RFID systems
Ph'D thesis of Gilles FRITZ and Omar ABDELMALEK
  • ANR LIESSE project "Laser-Induced fault Effects in Security-dedicated circuitS"
Industrial Partner: ST Microelectronics
Academic Partners: LIRMM, LCIS, TIMA, ENSME, ONERA  

Current PhD Students supervision:

  • Ihab ALASHAER, "Cross-layer Fault Analysis on Microprocessor Architecture", November 2020
  • Hiep Manh DO, "Design of Secure Tags using ECC", December 2019
  • Nikos Foivos POLYCHONOUS, "Supervisor Design for Critical Embedded Systems", December 2019
  • Amir ALIPOUR, "Machine Learning for Modeling of PUF", October 2019
  • Julie ROUX, "Robustness Evaluation of Critical System using Cross-Layer Analysis"', January 2018

Graduated PhD Students:

Teaching at Grenoble INP Esisar

Key words: Digital Design, VHDL, FPGA, VHDL-AMS, Functional Verification, Safety, Security

  • Advanced Digital Architectures
  • Verification and test of embedded secured systems
  • Design of Analog and Mixed Systems
  • Design of VLSI CMOS Integrated Circuits
  • Hardware/Software co-design
Head of the international master MISTRE Valence.

List of Publications

mise à jour le 5 octobre 2021

50, rue Barthélémy de Laffemas
BP54 26902 VALENCE Cedex 09 France
Tél : +33 (0)4 75 75 94 49
Université Grenoble Alpes