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Grenoble INP - LCIS 50 rue B. de Laffemas CS10054 26902 VALENCE Cedex 9 FRANCE
Personal Website : http://lcis.grenoble-inp.fr/themes/vincent-beroulle-home-page
Key words: Digital Design, VHDL, FPGA, Functional Verification, Safety, Security
Head of the international master MISTRE Valence
Key words: Security, Safety, FPGA Prototyping, Verification, Test, Fault Injection
Vincent Beroulle received an Engineer Degree from the National Polytechnical Institute of Grenoble (INPG) in 1996, and a Master Degree and a Ph.D in Microelectronics from the University of Montpellier II, respectively in 1999 and 2002. He is currently Professor at the Grenoble Institute of Technology. In the LCIS laboratory, he is head of the CTSYS team. In Grenoble INP - Esisar, he is head of the MISTRE Valence: an international master program on embedded system security and safety. His main interest concerns security and verification of complex integrated circuits and systems. In particular, his work deals with fault modeling and fault injection with emulation platforms with a specific focus on IoT and RFID technologies.
Date of update November 21, 2019
50, rue Barthélémy de Laffemas 